As the degree of integration of semiconductor integrated circuits increases, greater demands are placed on integrated circuit packaging and assembly. Common among these demands is a need for miniaturization of integrated circuit packages. This miniaturization forces critical consideration of package design criteria. For hermetic packaging, package and lid dimensions are squeezed from both sides, i.e. higher levels of integration resulting in larger semiconductor die sizes which must be accommodated by the package cavity, while integrated circuit users demand the greatest possible density of circuit functions per square inch of circuit board space, driving external package dimensions smaller. Given these demanding package design considerations, lid-to-package alignment accuracy plays a key role in package integrity.
Common techniques for locating integrated circuit package elements during encapsulation consist of two pieces of tooling: a boat that carries and locates the package or substrate, and an alignment cover that locates the other package element or lid during thermal processing, including encapsulation. This technique introduces several sources of variation in package/lid alignment, such as variation in package or substrate dimension which must be accommodated by the boat. This necessary clearance reduces the locational accuracy of the lid relative to the package. Similarly, the alignment cover's positional accuracy is determined by the clearance between its cavity dimension and the lid being located. Also, the relative position of the cover's cavity or lid alignment features to those alignment features of the boat affect package die alignment.